Semiconductor integrated circuit device

ABSTRACT

A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

Japan Priority Application 2006-331618, filed Dec. 8, 2006 including thespecification, drawings, claims and abstract, is incorporated herein byreference in its entirety. This application is a Continuation of U.S.application Ser. No. 12/817,914, filed Jun. 17, 2010, incorporatedherein by reference in its entirety, which is a Continuation of U.S.application Ser. No. 11/987,854, filed Dec. 5, 2007, incorporated hereinby reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuitdevice, and particularly to a semiconductor integrated circuit devicehaving a decoupling capacitor (on chip capacitor).

2. Description of Related Art

With increasing number of devices and higher speed of LSI (Large ScaleIntegration), the problem of power supply noise is becoming serious. Asa countermeasure against this power supply noise, the method ofconnecting a power source line and a ground line by a decouplingcapacitor is known. The decoupling capacitor is required to followvarious noises with different frequencies.

Meanwhile, the decoupling capacitor is playing an important role as anESD (Electrostatic Discharge) protection device. In recent years, thecountermeasure against ESD for the decoupling capacitor itself is posinga serious problem due to a thinner gate insulating film. Therefore, adecoupling capacitor which satisfies both aspects of the countermeasurefor noise and ESD is needed.

The techniques of reducing the power supply noise using conventionaldecoupling capacitors are explained here. Japanese Unexamined PatentApplication Publication No. 2006-101254 (Kajita) discloses the techniqueto form a resonant circuit and a low pass filter using a decouplingcapacitor so as to attempt reducing the noise of various frequencies. Inthe technique disclosed by Kajita, a power source line is resonatedcompulsorily by the resonant circuit formed of a decoupling capacitorand coil to concentrate noise near resonance frequency. Then, the noiseconcentrated near the resonance frequency is attenuated by the low passfilter formed of resistance and a capacitor.

Generally, a decoupling capacitor is disposed to a “vacant area” whereno other devices are not disposed, after disposing a circuit block. Achange in the circuit size and capacity to mount may cause insufficientnoise reduction effect by the decoupling capacitor. Therefore, JapaneseUnexamined Patent Application Publication No. 2006-040962 (Ogawa)discloses the method of disposing a decoupling capacitor in the chip.Specifically, the method is to secure a decoupling capacitor necessaryfor each unit area and efficiently carry out the disposing work.Moreover, Japanese Unexamined Patent Application Publication No.2001-284526 (Kasahara) discloses the technique to improve the frequencycharacteristic of MIM capacitance. Generally, the frequencycharacteristics are known to be influenced by the shape of a capacitor.

Next, the role of a decoupling capacitor as an ESD protection device isdescribed. FIG. 6 shows the configuration of a semiconductor integratedcircuit device using a conventional decoupling capacitor. As shown inFIG. 6, a plurality of decoupling capacitors C, which are MOScapacitances, are provided between a power source line connected to apower supply terminal Vcc and a ground line connected to a groundterminal GND. Note that in FIG. 6, the plurality of decouplingcapacitors are expressed as one decoupling capacitor.

Moreover, an ESD protection device (power supply protection device) isprovided between the power source line and the ground line and an ESDprotection device (input protection device) is provided between an inputterminal IN and the ground line. Here, a case is explained in whichelectrostatic surge is applied between the power supply terminal Vcc andthe ground terminal GND as an example. Although electrostatic surge isdischarged through a power supply protection device, it is also chargedto a decoupling capacitor immediately after the electrostatic surge isapplied so as to prevent an excessive current from flowing into thepower supply protection device.

Moreover, a case is explained in which electrostatic surge is appliedbetween the power supply terminal Vcc and the input terminal as anotherexample. The discharge path in this case is; power supply terminal Vcc<=> power supply protection device/decoupling capacitor <=> ground lineinput protection device <=> input terminal IN. Although whether theelectrostatic surge passes through the decoupling capacitor C, the powersupply protection device or both of them at the same time depends on thelayout, the decoupling capacitor C may be a discharge path.

In “DENGEN KURANPU NI KANSURU KOSATU” by Suzuki et al., November 2005,EOS/ESD/EMC Symposium, 15th RCJ Reliability Symposium Happyo Ronbunsyu,pp. 185-190, the relationship between a capacitance value of adecoupling capacitor and ESD robustness is shown when the decouplingcapacitor and a protection device (power supply protection device) existbetween a power supply terminal and a ground terminal. The techniquedisclosed by Suzuki et al. indicates that when static electricity isapplied between power supply and ground, as the decoupling capacitordoes not contribute to electrostatic discharge (ESD) if the capacitancevalue of the decoupling capacitor is about 1 pF, ESD robustness isdetermined by the power supply protection device. Moreover, Suzuki etal. indicate that if the capacitance value of the decoupling capacitoris large, about 40 nF, static charge is discharged through thedecoupling capacitor. The Suzuki et al. further indicate that if thecapacitance value of the decoupling is about 100 pF, which is between 1pF and 40 nF, the tolerated dose of the power supply protection devicedecreases under the influence of the operation of the decouplingcapacitor.

Moreover, although not shown in FIG. 6, the decoupling capacitor mayalso be a discharge path at the time of a CDM (Charged device model)test. When considering CDM discharge which is discharged from the powersupply terminal Vcc when a semiconductor device of P type substrate ischarging, charge by the side of a ground line potential (substratepotential) is discharged through the power supply protection device anda decoupling capacitor.

Japanese Unexamined Patent Application Publication No. 2001-060663(Horiguchi) discloses the necessity for the ESD protection of MOScapacitance and the configuration of a protection device. Horiguchiindicates that when there is a large potential difference between twoelectrodes of a MOS capacitance device at the time of a CDM test,protection devices must be provided to appropriate places in order toprotect the capacitance device. Moreover, Japanese Unexamined PatentApplication Publication No. 2003-86699 (Takamiya) illustrates an exampleof a ESD countermeasure for a decoupling capacitor itself.

By increasing number of devices and higher speed of LSI, diversificationof power supply noise and high frequency noise in each functional blockinside a chip are becoming a problem. It is necessary to take frequencycharacteristics into consideration like Kajita as the countermeasure forthese problems. However, as generated noises are different for eachcircuit, it cannot be supported by one resonant circuit and a filtercircuit. Moreover, Ogawa does not support the types of noises (frequencycharacteristics of a capacitor). Furthermore, although Kasahara takesthe frequency characteristics into consideration, Kasahara does not haveany suggestion concerning the arrangement of a decoupling capacitor in achip.

In addition, as indicated by Suzuki et al., since the capacitance valueof a decoupling capacitor influences ESD robustness, it must be designedtogether with ESD robustness of the protection device itself. However,such consideration has not been made for the arrangement of conventionaldecoupling capacitors.

Furthermore, by a thinner insulating film of a decoupling capacitor(gate insulating film in case of a MOS capacitance), ESD robustness ofthe decoupling capacitor itself has become a problem. Horiguchi andTakamiya indicate the necessity for protection of a MOS capacitancedevice. However, both ESD robustness of a decoupling capacitor and noisereduction have not simultaneously been taken into consideration.Especially for a LSI having many power supply and ground terminals,there are various capacitance values of decoupling capacitors betweenpower supply and ground. Therefore, the inventor has now discovered thata configuration which simultaneously satisfies three requirements ofnoise countermeasure, ESD robustness and ESD protection of a decouplingcapacitor itself has not been realized.

SUMMARY OF THE INVENTION

In one embodiment, a semiconductor integrated circuit device includes apower supply line connected to a power supply terminal, a ground lineconnected to a ground terminal and a plurality of capacitors connectedin parallel between the power supply line and the ground line. Theplurality of capacitors include a first capacitor arranged at a firstdistance from one of the terminals and a second capacitor arranged at asecond distance which is larger than the first distance from the one ofthe terminals, and the first capacitor has a larger area than the secondcapacitor. By having a large-shaped capacitance device near externalterminals where more current flows, it is possible to improve ESDrobustness of the capacitor itself. Furthermore, mounting a plurality ofcapacitors in different shapes enables to correspond to noise of variousfrequencies.

The present invention is able to provide a semiconductor integratedcircuit device having a decoupling capacitor capable of achieving boththe noise countermeasure of a circuit and ESD protection.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the presentinvention will be more apparent from the following description ofcertain preferred embodiments taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 shows the configuration of a semiconductor integrated circuitdevice according to a first embodiment;

FIG. 2 shows the configuration of a MOS capacitance device mounted tothe semiconductor integrated circuit device according to the firstembodiment;

FIG. 3 is a cross-sectional diagram taken along the line II-II of FIG.2;

FIG. 4 shows the configuration of a semiconductor integrated circuitdevice according to a second embodiment;

FIG. 5 shows the configuration of a semiconductor integrated circuitdevice according to a third embodiment;

FIG. 6 shows the configuration of a conventional semiconductorintegrated circuit device; and

FIG. 7 is a graph showing a relationship between a MOS capacitancedevice and ESD robustness.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will now he described herein with reference toillustrative embodiments. Those skilled in the art will recognize thatmany alternative embodiments can be accomplished using the teachings ofthe present invention and that the invention is not limited to theembodiments illustrated for explanatory purposes.

For the present invention, the inventor firstly investigated therelationship between MOS capacitance and ESD robustness. Then, theinventor has made the present invention based on the result. Therefore,firstly the relationship between the MOS capacitance and the ESDrobustness is described, which is a problem to be solved by the presentinvention. FIG. 7 shows the relationship between a capacitance device(MOS capacitance device) and ESD robustness (TLP (Transmission LinePulsing) tolerated dose) is shown in FIG. 7. In addition, those skilledin the art recognize that the TLP current value and the ESD robustnessare in proportionality relation.

Here, a MOS capacitance device having a gate oxide film of 5nm thicknessis manufactured as a capacitance device. In FIG. 7, the horizontal axisindicates the area (gate area) Sc of the MOS capacitance device by thelogarithmic axis. Moreover, the vertical axis indicates the TLP currentITLP by the linear axis. FIG. 7 indicates the following relationship.

ITLP∝a*Sc^(b) (a and b are constants)   (1)

Therefore, when ESD robustness is taken into consideration, it can beseen that the area of a MOS capacitance device must be given attention.That is, since a MOS capacitance device with a small area has low ESDrobustness, a measure to protect the MOS capacitance device itself by aprotection device or increase the area of the MOS capacitance device isrequired.

In the present invention, the shape of the MOS capacitance devicedisposed near an external terminal (a power supply terminal and a groundterminal) is enlarged. In addition, if a plurality of capacitancedevices are formed to increase the total capacitance without consideringthe shape of a MOS capacitance device, it can be thought that the areaof the MOS capacitance device will become large and area dependency asin the formula (1) will not be a problem. However, the abovementionedproblem cannot be solved in this way. Thus, it is not a problem ifcurrent flows equally to each MOS capacitance device, however inreality, current flowing nearby and far from the external terminal isdifferent and more current flows to a capacitance device near theexternal terminal. Therefore, the MOS capacitance device disposed nearthe external terminal is easy to be destroyed. Therefore, as in thepresent invention, the shape of the MOS capacitance device disposed nearthe external terminal (the power supply terminal and the groundterminal) is enlarged and the ESD robustness of the MOS capacitancedevice itself is improved.

Next, a solution for the problem of the power supply noise in thepresent invention is described. Here, a MOS capacitance device isdescribed having MOSFET structure in which a source, a drain and asubstrate potential are made to be the same potential and a gateelectrode as an opposite electrode. As disclosed in Japanese UnexaminedPatent Application Publication No. 2001-284526, the relationship betweenthe area of the MOS capacitance device and frequency has higherfrequency response as the gate area is smaller (gate length is shorter).Therefore, in the present invention, in order to correspond to the noiseof various frequencies, a plurality of capacitance devices are mountedso that the capacitance device in various shapes have necessarycapacitance values according to the noise.

Specifically, a power supply line and a ground line are respectivelydivided into a trunk line and a branch line, and a large MOS capacitancedevice (large capacity in general) is connected to the trunk line and asmall MOS capacitance device (small capacity in general) is connected tothe branch line. Hereafter, embodiments of the invention are describedin detail with reference to the drawings.

First Embodiment

A first embodiment of the present invention is explained with referenceto FIGS. 1 to 3. FIG. 1 shows the circuit configuration of asemiconductor integrated circuit device 10 according to this embodiment.Moreover, FIG. 2 is a plane view of a MOS capacitance device mounted tothe semiconductor integrated circuit device 10 of this embodiment. FIG.3 is a cross-sectional diagram taken along the line II-II of FIG. 2.Note that the internal circuit is omitted in FIG. 1.

As shown in FIG. 1, the semiconductor integrated circuit device 10 ofthis embodiment includes a power supply terminal Vcc, a ground terminalGND, a power supply line 11, a ground line 12, a power supply protectiondevice 13 and capacitors 1, 2 and 3. In this embodiment, the capacitors1, 2 and 3 are all formed of N type MOS capacitance devices. Note thatin this embodiment, although the example of a semiconductor integratedcircuit device having 3 capacitors is explained, it is not limited tothis. Moreover, the capacitors 1, 2 and 3 are made in the same way as annormal N type MOSFET.

The power supply line 11 is connected to the power supply terminal Vcc.Moreover, the ground line 12 is connected to the ground terminal GND.The power supply line 11 and the ground line 12 are formed to extend inthe same direction respectively from the power supply terminal Vcc andthe ground terminal GND. That is, the direction in which the powersupply line 11 is extended from the power supply terminal Vcc and thedirection in which the ground line 12 is extended from the groundterminal GND are the same. One electrode of the capacitors 1, 2 and 3 isrespectively connected to the power supply line 11. Moreover, the otherelectrode of the capacitors 1, 2 and 3 is respectively connected to theground line 12. Therefore, the plurality of capacitors 1, 2 and 3 areconnected in parallel between the power supply line 11 and the groundline 12.

The capacitor 2 is disposed to the power supply terminal Vcc and theground terminal GND side of the capacitor 3. Moreover, the capacitor 1is disposed to the power supply terminal and the ground terminal side ofthe capacitor 2. Specifically, the capacitor 1 is arranged at a firstdistance from one of the terminals and the capacitor 2 is arranged at asecond distance which is larger than the first distance from the one ofthe terminals. The capacitor 3 is arranged at a third distance which islarger than the second distance from the one of the terminals.Furthermore, the power supply protection device 13 is formed to thepower supply terminal Vcc and the ground terminal GND side of thecapacitor 1. The power supply protection device 13 is formed between thepower supply line 11 and the ground line 12. The power supply protectiondevice 13 is provided to prevent surge current from flowing into aninternal circuit, control the voltage applied to the internal circuitand protect the internal circuit from ESD.

FIGS. 2 and 3 show the configuration of the MOS capacitance deviceaccording to this embodiment. Although the capacitors 1, 2 and 3 allhave the configuration shown in FIGS. 2 and 3, the shapes are differentas described below. Firstly, the configuration of the MOS capacitancedevice is explained. As shown in FIG. 2, an N+ diffusion layer 15, an N+diffusion layer 16 and a gate electrode 17 arc formed over a P typesubstrate 14 to form the MOS capacitance device. As shown in FIG. 3, theN+ diffusion layers 15 and 16 arc disposed separately over the P typesubstrate 14. A gate insulating film 18 is formed over the substratesurface between the N+ diffusion layers 15 and 16. The gate electrode 17is formed over the gate insulating film 18. Each of the N+ diffusionlayers 15 and 16 is connected to plug contacts 19. The plug contacts 19are connected to the ground line 12. This is the same as the one inwhich a source and a drain of a normal MOSFET are grounded. On the otherhand, the gate electrode 17 is connected to the power supply line 11.

Next, the difference in the shape of each capacitor is explained. Asshown in FIG. 2, width of the MOS capacitance device shall be W andlength shall be L. In this document, to express the size of the MOScapacitance device, the expressions of the gate width W and the gatelength L for a MOSFET are used for convenience. That is, the length L ofthe capacitance device is the gate length of the gate electrode 17, andthe width W of the capacitance device is the width of the gate electrode17 which overlaps with the N+ diffusion layers 15 and 16. The length Lof each capacitance device is formed to be shorter as it is farther fromthe power supply terminal Vcc and the ground terminal GND. Therefore,the length L2 of the capacitor 2 is shorter than the length L1 of thecapacitor 1. Moreover, the length L3 of the capacitor 3 is shorter thanthe length L2 of the capacitor 2.

Note that in this embodiment, each width of the capacitors 1, 2 and 3 isequal. Therefore, the areas (L×W) of the capacitors 1, 2 and 3 arelarger by the side of the power supply terminal Vcc and the groundterminal GND. More specifically, the areas of the capacitors 1, 2 and 3become smaller inversely proportional to the distance from the one ofthe terminals. That is, the area of the capacitor 1 is larger than thearea of the capacitor 2, and the area of the capacitor 2 is larger thanthe area of the capacitor 3.

For example, the following combination can be made; the width W of thecapacitors 1, 2 and 3 are made to be equal, which is 50 μm, the lengthL1 of the capacitor 1 is 50 to 100 um, the length of the capacitor 2 is10 to 20 μm and the length L3 of the capacitor 3 is 1 to 5 μm. In orderto have such combination, the gate width of the capacitance devicesforming each capacitor may be formed to have a difference of severalfold to one order of magnitude.

Note that in FIG. 1, each capacitor is indicated by one capacitorsymbol. However in reality, the capacitors 1, 2 and 3 are formed as acapacitance device group having a plurality of capacitance devices ofalmost the same shape. Here, the capacitor 1 is formed of a capacitancedevice group of N1 capacitance devices with a capacitance value C1, thecapacitor 2 is formed of a capacitance device group of N2 capacitancedevices with a capacitance value C2 and the capacitor C3 is formed of acapacitance device group of N3 capacitance devices with a capacitancevalue C3. The capacitor 1 has the configuration in which N1 capacitancedevices having the capacitance value C1 and almost the same shape areconnected in parallel. Moreover, the capacitor 2 has the configurationin which N2 capacitance devices having the capacitance value C2 andalmost the same shape are connected in parallel. Furthermore, acapacitor 3 has the configuration in which N3 capacitance devices havingthe capacitance value C3 and almost the same shape are connected inparallel. The capacitors may be formed so that the total capacitancevalue of each capacitance device may become smaller as it is fartherfrom the power supply terminal Vcc and the ground terminal GND. That is,the capacitors may be formed to be C1*N1>C2*N2>C3*N3.

Moreover, the numbers N1, N2 and N3 of each capacitance devices may beadjusted so that the total capacitance value of the 3 capacitance devicegroups (the capacitors 1, 2 and 3) may be equal. That is, it can beadjusted to be C1*N1=C2*N2=C3*N3. The length L and the width W of thecapacitance device and the total capacitance value of each capacitor(the number N of the capacitance device) can be determined inconsideration of the circuit size and the characteristics of generatednoise. It is needless to say that capacitance device groups with 3 ormore kinds of different shapes may be provided.

A MOS capacitance device is known to have gate length dependency andresponse to noise with high frequency as the gate length is shorter(gate area is smaller). The present invention enables to follow aplurality of noise characteristics by providing MOS capacitance devicesof several shapes. Therefore, noise between power supply and ground canbe effectively reduced.

Moreover, ESD robustness of a MOS capacitance device has area dependencyand known to have lower ESD robustness as the area is smaller. In thepresent invention, the shape of the MOS capacitance device formed nearthe external terminal where more current flows is enlarged. Therefore,the MOS capacitance device itself is hard to be destroyed by ESD.Therefore, the present invention achieves to reduce noise and improveESD robustness at the same time by optimizing the shape and thearrangement of the MOS capacitance device.

Note that although in the abovementioned example, the width W of thecapacitance devices were made to be the same and the length L of thecapacitance device is made to be smaller as it is farther from the powersupply terminal Vcc and the ground terminal GND, it is not limited tothis. For example, the length L of the capacitance device may made to beconstant and the width W of each capacitance device may made to besmaller as it is farther from the power supply terminal Vcc and theground terminal GND. Moreover, both of the length L and the width W ofthe capacitance device may made to be smaller as it is farther from thepower supply terminal Vcc and the ground terminal GND. That is, the areaof each capacitance device needs to be smaller as it is farther from thepower supply terminal Vcc and the ground terminal GND. Therefore, theplurality of capacitors 1, 2 and 3 may be almost square or almostrectangular shape.

Second Embodiment

A semiconductor integrated circuit device 20 according to a secondembodiment of the present invention is explained with reference to FIG.4. FIG. 4 shows the configuration of the semiconductor integratedcircuit device 20 according to this embodiment. There are many powersupply lines and ground lines in the whole LSI. The power supply lineand the ground line each have a trunk line and its branch line. As shownin FIG. 4, the semiconductor integrated circuit device 20 of thisembodiment includes a power supply terminal Vcc, a ground terminal GND,a power supply line 21, a ground line 22 and a functional circuit block29. The power supply line 21 includes a trunk line 23 and a branch line25. Moreover, the ground line 22 includes a trunk line 24 and a branchline 26. The trunk line 23 is extended from the power supply terminalVcc. Then, the branch line 25 is extended and branches from the trunkline 23. On the other hand, the trunk line 24 is extended from theground terminal GND. Then, the branch line 26 is extended and branchesfrom the trunk line 24.

In this embodiment, an example is illustrated in which the power supplyline 21 and the ground line 22 provide a decoupling capacitor to theplace indicated as A in FIG. 4 for the trunk lines (between the trunklines 23 and 24) and to the place indicated as B for the branch lines(between the branch lines 25 and 26). A capacitor 27 is formed betweenthe trunk lines 23 and 24. Moreover, a capacitor 28 is formed betweenthe branch lines 25 and 26. The capacitor 27 has a gate area larger thanthe capacitor 28. In this embodiment, the gate length L1 of thecapacitor 27 is longer than the gate length L2 of the capacitor 28.

The distance between the branch lines 25 and 26 and the power supplyterminal Vcc and the ground terminal GND is longer than the distancebetween the trunk lines 23 and 24 and the power supply terminal Vcc andthe ground terminal GND. Moreover, as noise of many circuit blocks issuperimposed near the power supply terminal Vcc and the ground terminalGND and the trunk lines 23 and 24, noise frequency often cannot bespecified. However there are a lot of low frequency noises generated.Accordingly, the area of the capacitor 27 formed near the power supplyterminal and the ground terminal GND is increased (increase the gatelength). This enables to suppress from destroying the capacitor 27 byESD and effectively reduce the low frequency noise.

Moreover, both or either of the branch lines connected to the powersupply line and the ground line is connected to the functional circuitblock 29. In this embodiment, the functional circuit block 29 is formedbetween the branch lines 25 and 26. Although depending on the operation,the noise generated from the functional circuit block 29 often includeshigh frequency component. Moreover, since the capacitor 28 between thebranch lines 25 and 26 is far from the power supply terminal Vcc and theground terminal GND, it has a small risk of ESD breakdown. Therefore,the gate length of the capacitor 28 formed between the branch lines 25and 26 is shortened so as to effectively reduce the noise generated fromthe functional circuit block connected to the branch lines. Moreover, ifnoise-frequency can be specified, a MOS capacitance device can be formedto respond to the frequency well.

As described above, in this embodiment, by having a larger decouplingcapacitor connected to the trunk line than the decoupling capacitorconnected to the branch line, it is possible to achieve ESDcountermeasure for the decoupling capacitors themselves and improvenoise-frequency response characteristics.

Note that in FIG. 4, the capacitors 27 and 28 are expressed with onecircuit symbol. However in reality, the capacitors 27 and 28 are formedas a capacitance device group formed of a plurality of MOS capacitancedevices.

Moreover, many functional circuits are mounted to the actual product.Therefore, when providing a decoupling capacitor between the powersupply line 21 and the ground line 22 including the branch linessupplied to a plurality of functional circuits F1, F2, F3 . . . , thedecoupling capacitor can be formed according to the noisecharacteristics of the functional circuits F1, F2 and F3. To be morespecific, a plurality of capacitance devices with a capacitance value C1and an area L1*W1 are formed corresponding to the functional circuit F1,a plurality of capacitance devices with a capacitance value C2 and anarea L2*W2 are formed corresponding to the functional circuit F2 and aplurality of capacitance devices with a capacitance value C3 and an areaL3*W3 are formed corresponding to the functional circuit F3. Moreover,the decoupling capacitor provided between the trunk lines 23 and 24 willhave a longer gate length and larger area than those formed between eachbranch lines of the power supply line and the ground line. As describedabove, by dispersing MOS capacitance devices having desired shapesinside a chip, it is possible to achieve both ESD countermeasure for theMOS capacitance devices themselves and reduce noise of the functionalcircuit block 29.

Third Embodiment

A semiconductor integrated circuit device 30 according to a thirdembodiment of the present invention is explained with reference to FIG.5. FIG. 5 shows the configuration of the semiconductor integratedcircuit device 30 of this embodiment. A difference in this embodimentfrom the first embodiment shown in FIG. 1 is the locating position ofthe power supply terminal Vcc and the ground line GND.

As shown in FIG. 5, a power supply line 31 extended from the powersupply terminal Vcc is formed toward the ground terminal GND side.Moreover, a ground line 32 extended from ground terminal GND is formedtoward the power supply terminal Vcc side. Between the power supply line31 and the ground line 32, a power supply protection device 33,capacitors 34, 35, and 36 and a power supply protection device 37 areprovided from the ground terminal GND side to the power supply terminalVcc side. That is, the distance from the power supply terminal Vcc tothe capacitor 34 differs from the distance from the ground terminal GNDto the capacitor 34. Moreover, the distance from the power supplyterminal Vcc to the capacitor 36 differs from the distance from theground terminal GND to the capacitor 36.

Also in this embodiment, the area of each capacitor is formed to besmaller as it is farther from external terminals (the power supplyterminal Vcc and the ground terminal GND). In this embodiment, the powersupply terminal Vcc and the ground terminal GND are formed in theopposite side. Therefore, the area of the capacitor 36 provided near thepower supply terminal Vcc is larger than the area of the capacitor 35.Moreover, the area of the capacitor 34 provided near the ground terminalGND is larger than the capacitor 35.

Specifically, the length L of each capacitance device is formed to beshorter as it is farther from the power supply terminal Vcc or theground terminal GND. Thus, the length L2 of the capacitor 35 is shorterthan the length L1 of the capacitor 34. Moreover, the length L2 of thecapacitor 35 is shorter than the length L3 of the capacitor 36. Notethat as described above, the width W or both the width and the length ofeach capacitance device may be formed to be shorter as it is fartherfrom the power supply terminal Vcc or the ground terminal GND.

In this way, if the power supply terminal Vcc and the ground terminalGND are positioned opposite when viewed from each other's wiringdirection, the area of the decoupling capacitor disposed to the sidenear the external terminals (the power supply terminal Vcc and theground terminal GND) is made to be larger than the decoupling capacitordisposed far from the external terminals. Thus, ESD robustness can beimproved by forming a MOS capacitance device with a large area near theexternal terminals. Moreover, since various shaped MOS capacitancedevices are formed in one chip, noise of various frequencies can bereduced.

In addition, as mentioned above, the capacitors 34, 35 and 36 may all beformed as a capacitance device group having a plurality of capacitancedevices in almost the same shape. In such case, the capacitor 34 shallbe formed of capacitance device group of N1 capacitance devices with acapacitance value Cl, the capacitor 35 shall be formed of capacitancedevice group of N2 capacitance devices with a capacitance value C2 andthe capacitor 36 shall be formed of capacitance device group of N3capacitance devices with a capacitance value C3. Each capacitance deviceis formed to satisfy C1>C2<C3. Moreover, the capacitance devices may beformed to satisfy so that the total capacitance value of eachcapacitance device group satisfies the relationship ofC1*N1>C2*N2<C3*N3. Otherwise, the numbers N1, N2 and N3 of eachcapacitance may be adjusted so that the total capacitance value of the 3capacitance device groups (the capacitors 34, 35 and 36) may be equal.Thus, they may be adjusted to be C1*N1=C2*N2=C3*N3.

As explained above, it is possible to achieve noise reduction effect andeliminate the risk of ESD breakdown for capacitance device itself byoptimizing the shape of the decoupling capacitor and the locatingposition inside a chip.

Note that in the above explanation, an example is explained in which theplurality of capacitors are formed of MOS capacitance devices, howeverit is not limited to this. For example, it is also possible to use a MIScapacitance device, a MIM capacitance device, etc. as a capacitor.

It is apparent that the present invention is not limited to the aboveembodiments, but may be modified and changed without departing from thescope and spirit of the invention.

1. A semiconductor integrated circuit device comprising: a first powersupply line coupled to a first power supply terminal, the first powersupply line having a first node, a second node and a third node in thisorder from the first power supply terminal; a second power supply linecoupled to a second power supply terminal, the second power supply linehaving a fourth node, a fifth node and a sixth node in this order fromthe second power supply terminal; a first capacitor arranged between thefirst node and the sixth node; a second capacitor arranged between thesecond node and the fifth node; a third capacitor arranged between thethird node and the fourth node; wherein a capacitance value of thesecond capacitor is smaller than that of the first and third capacitors,wherein the first node is connected to the second node on the firstpower supply line without coupling the first, second and thirdcapacitors, the second node is connected to the third node on the firstpower supply line without coupling the first, second and thirdcapacitors, the fourth node is connected to the fifth node on the secondpower supply line without coupling the first, second and thirdcapacitors, and the fifth node is connected to the sixth node on thesecond power supply line without coupling the first, second and thirdcapacitors.
 2. The semiconductor integrated circuit device according toclaim 1, further comprising a power supply protection device that isprovided between the first and second power supply lines.
 3. Thesemiconductor integrated circuit device according to claim 1, whereinthe first capacitor is formed of N1 capacitance devices having acapacitance value of C1 each, the second capacitor is formed of N2capacitance devices having a capacitance value of C2 each, and thesemiconductor integrated circuit device satisfies a relationship ofC1*N1>C2*N2.
 4. The semiconductor integrated circuit device according toclaim 3, wherein the capacitance value of C1 is larger than thecapacitance value of C2.
 5. The semiconductor integrated circuit deviceaccording to claim 1, wherein areas of the first and second capacitorsare inversely proportional to the distance from the first power supplyterminal.
 6. The semiconductor integrated circuit device according toclaim 5, wherein the first, second and third capacitors are each formedof a plurality of capacitance devices, and the total capacitance valuesof the plurality of capacitance devices of the second capacitor are madeto be smaller than the total capacitance values of the plurality ofcapacitance devices of the first capacitor and smaller than the totalcapacitance values of the plurality of capacitance devices of the thirdcapacitor.
 7. The semiconductor integrated circuit device according toclaim 1, further comprising a functional circuit block supplied with apotential via the first power supply line and the second power supplyline, wherein the second capacitor is provided near the functionalcircuit block.
 8. The semiconductor integrated circuit device accordingto claim 7, further comprising a plurality of functional circuit blockssupplied with a potential via the first power supply line and the secondpower supply line, wherein the first, second and third capacitors areformed to correspond to the plurality of functional circuit blocks. 9.The semiconductor integrated circuit device according to claim 1,wherein the first, second and third capacitors include a MOS capacitancedevice, a MIS capacitance device or a MIM capacitance device.
 10. Thesemiconductor integrated circuit device according to claim 1, whereinthe first, second and third capacitors have function of a decouplingcapacitor and a static electricity protection function.
 11. Thesemiconductor integrated circuit device according to claim 1, whereinelectrodes of the first, second and third capacitors are square shape.12. The semiconductor integrated circuit device according to claim 1,wherein electrodes of the first, second and third capacitors arerectangle shape.
 13. The semiconductor integrated circuit deviceaccording to claim 1, wherein at least either a length or a width of thethird capacitor is larger than that of the second capacitor.
 14. Thesemiconductor integrated circuit device according to claim 1, whereinthe third capacitor is formed of N3 capacitance devices having acapacitance value of C3 each, the second capacitor is formed of N2capacitance devices having a capacitance value of C2 each, and thesemiconductor integrated circuit device satisfies a relationship ofC3*N3>C2*N2.
 15. The semiconductor integrated circuit device accordingto claim 14, wherein the capacitance value of C3 is larger than thecapacitance value of C2.
 16. The semiconductor integrated circuit deviceaccording to claim 1, wherein areas of the third and second capacitorsare inversely proportional to the distance from the second power supplyterminal.
 17. The semiconductor integrated circuit device according toclaim 1, wherein the first power supply line extended from the firstpower supply terminal is formed toward the second power supply terminal,and the second power supply line extended from the second power supplyterminal is formed toward the first power supply terminal.
 18. Thesemiconductor integrated circuit device according to claim 1, whereinthe first, second and third capacitors are connected in parallel betweenthe first and second power supply lines.